/****************************************************************************
 * vendor/semidrive/chips/common/include/arm_reg.h
 *
 * Licensed to the Apache Software Foundation (ASF) under one or more
 * contributor license agreements.  See the NOTICE file distributed with
 * this work for additional information regarding copyright ownership.  The
 * ASF licenses this file to you under the Apache License, Version 2.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at
 *
 *   http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
 * License for the specific language governing permissions and limitations
 * under the License.
 *
 ****************************************************************************/
#ifndef __CHIPS_E3650_COMMON_MPU_REG_H
#define __CHIPS_E3650_COMMON_MPU_REG_H

#define MPU_BIT(x, n)            (x & (1UL << (n)))

#define MPU_BITS_SHIFT(x, h, l) \
    (((x) >> (l)) & ((1UL << ((h) - (l) + 1)) - 1UL))

#define MPU_MASK(h, l) \
    (((~0U) << (l)) & ((~0U) >> (31 - (h))))


// MPUIR (MPU Type Register)
// [15:8] DREGION: number of programmable regions
#define MPUIR_DREGION(r)        MPU_BITS_SHIFT(r, 15, 8)

// PRSELR (Protection Region Selection Register)
// [4:0] REGION: The number of current region visible in PRBAR and PRBLR
#define MPU_PRSELR_REGION(r)    MPU_BITS_SHIFT(r, 7, 0)

#define MPU_PRSELR_MASK_REGION  MPU_MASK(7, 0)

// PRBAR (Protection Region Base Address Register)
// [0] XN: Execute-never
#define MPU_PRBAR_MASK_XN       MPU_MASK(0, 0)
// [2:1] AP: Access Permission bits
#define MPU_PRBAR_MASK_AP       MPU_MASK(2, 1)
// [4:3] SH: Shareability field
#define MPU_PRBAR_MASK_SH       MPU_MASK(4, 3)
// [31:6] BASE: Base address of selected MPU memory region
#define MPU_PRBAR_MASK_BASE     MPU_MASK(31, 6)

// PRLAR (Protection Region Limit Address Register)
// [0] EN: Region-enable
#define MPU_PRLAR_MASK_EN       MPU_MASK(0, 0)
// [3:1] AttrIndx: Indexes a set of attributes in one of MAIRx registers
#define MPU_PRLAR_MASK_ATTRINDX MPU_MASK(3, 1)
// [31:6] LIMIT: Limit address of selected MPU memory region (postfixed with 0x3F)
#define MPU_PRLAR_MASK_LIMIT    MPU_MASK(31, 6)

#endif // __CHIPS_E3650_COMMON_MPU_REG_H
